Method and device for correction of ternary stored binary data

ABSTRACT

The invention relates to a device and a method for storing binary data in a storage device, in which the binary data is transformed to and stored as ternary data. The storage device uses memory cells capable of storing three states. The device and method furthermore are configured to identify and correct falsified ternary data when reading and outputting the data from storage device.

FIELD

The invention relates to a method and device for storing data, particularly for storing binary data in a memory using ternary storage. A method and corresponding circuitry are provided allowing the correction of stored binary data.

BACKGROUND

Data processing systems of today operate on data represented to any processing device in a binary format. Storage of these data takes place in a memory device typically using binary storage systems comprising storage cells. Typically each storage cell stores one bit, i.e. the storage cell is capable of storing two distinguishable states representing the states of the bit, i.e. either one or zero. A stream of binary data that is to be stored can be passed to a storage device for storing. The storage device is adapted and configured to set the memory cells corresponding to the input data stream when receiving the data for storing and to read the data from the memory cells upon request.

However the data read out from a memory can differ from the original data, i.e. the data that were provided for storing for variable reasons. In one example a storage cell may be faulty.

Numerous algorithms and corresponding solutions for identifying and correcting bit errors in stored data are known to prevent any falsification of data when reading stored data from binary memory cells.

Modern memory devices may use ternary memory or storage cells, i.e. cells adapted and configured for storing data, wherein each cell is adapted and configured to distinguish between three states. These memories may be used in combination with binary processing devices that provide binary data, i.e. wherein the information is represented in bits, each bit representing a binary value. So when storing binary data in a ternary memory device, i.e. a device using ternary storage cells, there must be some arrangement in the memory device not only for converting the binary to ternary data upon storage and for converting ternary to binary data when reading, but also for providing correction means to ensure that the read out data equals the data provided upon storing.

BRIEF DESCRIPTION OF THE FIGURES

The following figures shall illustrate the invention, wherein

FIG. 1 depicts an encoder;

FIG. 2 depicts a circuit arrangement for storing data sequences;

FIG. 3 depicts circuitry for correcting an error;

FIG. 4 depicts an arrangement of the circuitry depicted in FIGS. 1-3;

FIG. 5 depicts an embodiment of a circuit arrangement for storing data sequences;

FIGS. 6 a and 6 b depict embodiments of circuitry for transforming binary to ternary values;

FIGS. 7 a and 7 b depict embodiments of circuitry for transforming ternary to binary values;

FIGS. 8 a, 8 b and 8 c depict embodiments of implementations of partial circuit F;

FIG. 9 depicts a partial circuit; and

FIG. 10 depicts circuitry for error recognition.

DETAILED DESCRIPTION

The invention will now be described by means of embodiments. Note that the embodiments shall be understood as illustration only but not restricting the invention.

FIG. 1 illustrates an encoder Cod 11 encoding a binary data sequence u=u₁, . . . , u_(k) of k bits, wherein, k≧2, to an encoded binary data sequence x=x₁, . . . , x_(n) of n bits with n>k corresponding to a linear code C.

The linear code C may, as is usual, be described by a (k, n) generator matrix G with k rows and n columns, and by a (n−k, n) parity check matrix H, also referred to as H-matrix. The encoded binary data sequence x is determined from the binary data sequence u by x=(x ₁ , . . . , x _(n))=(u ₁ , . . . , u _(k))·G=u≠G  (1)

The k-bit data sequence u=u₁, . . . , u_(k) is available at the k-bit input line 12 of the encoder Cod 11, and the data sequence x=x₁, . . . , x_(n) determined according to equation (1) is output on the n-bit output line 13.

FIG. 2 illustrates a block diagram of a circuit arrangement Schspei 21 for storing data sequences. The circuit arrangement Schspei 21 comprises a data input 22 of at least n bits for the input of a binary data sequence x=x₁, . . . , x_(n) of word size n, an address input 24 for the input of a binary address a=a₁, . . . , a_(l) with l address bits, wherein l≧2, and a data output 23 of at least n bits for the output of an n-bit binary data sequence x′=x′₁, . . . , x′_(n). The data sequence x is encoded by using a code C. Additional control signals such as, for instance, the read signal and the write signal that are common for memory circuits and are known to a person skilled in the art are not illustrated in FIG. 2.

The circuit arrangement Schspei 21 is configured such that it is possible to write a binary data sequence x under an address a, to store corresponding values, and to read out a binary data sequence at a later point in time, for instance, also under the address a. The binary data available at the inputs are transformed to analog values in the circuit arrangement Schspei and stored as analog values, for example voltages or electric charges, in memory cells. These analog values may, depending on the belonging of the analog value to three different intervals, be interpreted as ternary values, as is, for instance, proposed in P. J. Krick, THREE-STATE MNOS FET MEMORY ARRAY, IBM technical disclosure bulletin, vol. 18, 12, 1976, pp. 4192-4193. The stored values may be designated as analog values in general and, if one intends to emphasize their belonging to the three intervals considered, also as ternary values. The value stored in a memory cell is also referred to as the condition of the memory cell.

On reading out, the ternary values stored are re-transformed to binary values and read out as binary values, so that the circuit arrangement Schspei 21 behaves in its external behavior like a binary memory, although the values are internally stored as ternary values.

When data is stored in the circuit arrangement Schspei, it is possible that these data are modified incorrectly, so that a binary data sequence x=x₁, . . . , x_(n) written under the address a, and which is stored in a ternary manner in the circuit arrangement, differs from a binary data sequence x′=x′₁, . . . , x′_(n) read out under the same address after a certain time. So if x=x′ applies, no error has occurred, but if x≠x′ applies, then an error has occurred. If a stored ternary value changes due to an error, this error in a ternary value may have the effect that one bit or several bits in a read-out binary data sequence change. A single error in a ternary, stored value may result in a multi bit error in the binary data sequence.

So far, no circuit arrangement and no method for error correction are known which enable one to correct those single bit and multi bit errors in the read-out binary data sequences that occur due to single errors in the ternary stored values.

In one embodiment, the present invention serves to correct single bit and multi bit errors in the read-out binary data sequences that occur due to single errors in the stored ternary data.

If an error occurs in the stored data, the read-out binary data sequence x′ differs from the corresponding written binary data sequence x. Usually, the bit-wise difference of x and x′ is designated as an error vector e that is determined as e=e ₁ , . . . , e _(n) =x ₁ ⊕x′ ₁ , . . . , x _(n) ⊕x′ _(n) =x⊕x′ wherein ⊕ designates the addition modulo 2 (or the logic function antivalence or XOR). For the components e_(i) of the error vector e there applies that e_(i)=1 if x_(i)≠x′_(i). Similarly we have e_(i)=0 if x_(i)=x′_(i).

FIG. 3 illustrates a circuit arrangement for error correction, referred to as corrector 38. The corrector 38 includes a syndrome generator Syndr 31, a decoder Dec 32, and an XOR circuit 33.

The syndrome generator Syndr 31 is configured to generate from the binary sequence x′=x′₁, . . . , x′_(n) a q-component error syndrome s=s₁, . . . , s_(q) with q=n−k according to the relation s ^(T)=(s ₁ , . . . , s _(q))^(T) =H·(x′ ₁ , . . . , x′ _(n))^(T) =H·x′ ^(T)  (2) H is the H-matrix, i.e. the parity check matrix, (with q rows and n columns) of the code C.

Decoder circuitry DEC 32 is configured to generate an error vector e=e₁, . . . , e_(n) for the correction of the possibly incorrect bit sequence x′ to the corrected bit sequence x^(c)=x^(c) ₁, . . . , x^(c) _(n) from the error syndrome s=s₁ . . . , s_(q) of the length q, wherein the correction is performed according to the relation x ^(c) =x ^(c) ₁ , . . . , x ^(c) _(n) =x′ ₁ ⊕e ₁ , . . . , x′ _(n) ⊕e _(n) =x′⊕x ^(c)  (3) wherein s^(T) is a q-component column vector with the components s₁, . . . , s_(q), and (x′₁, . . . , x_(n))^(T) is an n-component column vector.

If the error occurred is an error correctable by the used code C, there applies x ^(c) =x′⊕e=x, and the error is corrected properly.

The circuit arrangement for error correction pursuant to FIG. 3 will now be described in more detail.

The line 34 carrying the binary sequence x′=x′₁, . . . , x′_(n) is both coupled to the n-bit input of the syndrome generator Syndr 31 and to an n-bit first input of the XOR circuit 33. The q=n−k bit output line 35 of the syndrome generator Syndr 31 which carries the error syndrome s=s₁, . . . , s_(q) is coupled to the input of the decoder Dec 32. The n-bit output line 36 of the decoder 32 which carries the n components of the error vector e=e₁, . . . , e_(n) is connected in the correct position to the second, n-bit input of the XOR circuit 33 whose n-bit output carries the components x^(c) ₁, . . . , x^(c) _(n) of the binary sequence x^(c). The XOR circuit 33 is implemented in one embodiment by n parallel 2-input XOR gates with one output each.

FIG. 4 illustrates how the partial circuits illustrated in FIGS. 1, 2, and 3 may be connected to form a complete circuit enabling correction of storage errors according to one embodiment.

The circuit arrangement of FIG. 4 includes an encoder 41 (11 in FIG. 1), a circuit arrangement Schspei 42 (21 in FIG. 2) for storing data sequences, a corrector 43 (38 in FIG. 3) comprising a series connection of a syndrome generator Syndr 45 (31 in FIG. 3) and a decoder Dec 46 (32 in FIG. 3), and an XOR circuit 44 (33 in FIG. 3).

The k-bit input line 47 carrying the data sequence u=u₁, . . . , u_(k) is coupled to the input of the encoder 41. The n-bit output 48 of encoder 41 carries coded data sequence x=x₁, . . . , x_(n) and is coupled to the input of the circuit arrangement Schspei 42. The n-bit output 49 of the circuit arrangement Schspei 42 which carries the data sequence x′=x′₁, . . . , x′_(n) is coupled to the input of the syndrome generator Syndr 45 and to the first input of the XOR circuit 44. The output 410 of the syndrome generator Syndr 45 which carries the n−k=q bit error syndrome s is coupled to the input of the decoder Dec 46, which in turn is coupled with its output line 411 to the second input of the XOR circuit 44. The n-bit error vector e=e₁, . . . , e_(n) is output on output line 411 of the decoder Dec.

The n-bit output 412 of the XOR circuit 44 carries the corrected binary sequence x^(c)=x^(c) ₁, . . . , x^(c) _(n).

In one embodiment it is provided that only a subset of n′ bits of the n bits with n′≦n of the binary sequence x′ is corrected. Then, it is only necessary that the decoder Dec 46 provides only a subset of n′ components of the error vector e.

FIG. 5 illustrates an embodiment of a circuit arrangement Schspei 21 for storing data sequences. It comprises a circuit TrBT 51 for transforming binary sequences to analog sequences representing ternary signals, i.e. ternary sequences. Memory 52 is referred to as ternary memory that is adapted and configured to store sequences whose components are analog signals representing ternary signals. Circuit TrTB 53 is adapted and configured to transform analog sequences to binary sequences, wherein the components of the analog sequences represent ternary signals.

Analog signals representing ternary values or conditions are also simply referred to as ternary values or ternary conditions. Correspondingly, the circuits TrBT and TrTB are referred to as a circuit for transforming binary sequences to ternary sequences or signals and as a circuit for transforming ternary sequences to binary sequences or signals.

At the n-bit input line 54 of the circuit TrBT 51, n binary values x₁, . . . , x_(n) are provided. These are transformed by circuit 51 to a sequence of 2·m ternary signals A¹, B¹, . . . , A^(m), B^(m) and are output at the 2·m outputs 55 thereof. These 2-m outputs 55 are coupled to the data inputs of the ternary memory 52 to be stored in this memory under an address a available at the address input 57. If n is divisible by 3 without remainder, then m=n/3. If n is not divisible by 3 without remainder, the binary sequence x=x₁, . . . , x_(n) may be supplemented by one further or two further bits which are, for instance, constantly equal to 0, to a binary sequence x₁, x₂, . . . , x_(n′), with n′ components, so that n′ is divisible by 3 without remainder. The supplemented bits may, for instance, be chosen to be constantly equal to 0.

If the ternary data stored in the ternary memory 52 are read under the address a that is available on the address line 57 of the ternary memory, the ternary data A¹′, B¹′, . . . , A^(m′), B^(m′) are output on the 2·m data outputs 58 of the memory 52. Due to an error, possibly caused by radiation or by a gradual loss of charge or other reasons, the data written in the memory may be erroneous.

If no error exists, there applies A ¹ ,B ¹ , . . . , A ^(m) ,B ^(m) =A ¹ ′,B ¹ ′, . . . , A ^(m) ′,B ^(m)′ and in the case of an error there applies A ¹ ,B ¹ , . . . , A ^(m) ,B ^(m) ≠A ^(1′) ,B ^(1′) , . . . , A ^(m′) ,B ^(m′).

The 2m-bit output line 58 of ternary memory 52 is coupled to 2m analog inputs of circuit TrTB 53. Circuit TrTB 53 transforms ternary values A¹′, B¹′, . . . , A^(m)′, B^(m)′ to binary values x′₁, . . . , x′_(n) that are output on the n-bit output 56 of circuit TrTB 53.

FIG. 6 a and FIG. 6 b illustrate embodiments of the circuit TrBT 51 for transforming a binary sequence x₁, . . . , x_(n) of length n to a sequence A¹, B¹, . . . , A^(m), B^(m) of length 2·m of analog data representing ternary values. These ternary values are stored in the memory cells of the ternary memory 52. The analog value representing the ternary value stored in a memory cell is also referred to as the condition of the memory cell. The analog values A and B may be voltage values. In a non-volatile memory this is, for instance, the threshold voltage of the memory cell which is determined by the charging condition on the floating gate. Other physical quantities may, however, also be taken into consideration. In the instant embodiment, A and B are intended to be voltage values.

Depending on the fact in which of three predetermined intervals W₀, W₁, W₂ the values A, B are positioned, these analog values are referred to as A₀, A₁, A₂ or B₀, B₁, B₂, respectively. Thus, if AεW₁ applies for i=0, 1, 2, the analog signal A represents the ternary value A₁. If BεW₁ applies for j=0, 1, 2, the analog signal B represents the ternary value B_(j).

FIG. 6 a and FIG. 6 b illustrate how a sequence of binary signals x₁, . . . , x_(n) can be transformed to a sequence of ternary signals A¹, B¹, . . . , A^(m), B^(m).

Circuit TrBT 51 of FIG. 6 a is composed of partial circuits F₁ 611, F₂ 612, . . . , F_(m) 61 m. These m partial circuits F_(i), i=1, . . . , m each implement a direct mapping F_(i) of three-digit binary triples to 2-digit analog values whose components represent a ternary value depending on their belonging to one of the three intervals W₀, W₁, W₂. It is not necessary that the three binary values forming a triple of binary values, and which is transformed to a tuple of two ternary values, are directly consecutive in the sequence x=x₁, . . . , x_(n). It is, for instance, possible that the binary values x₁, x₁₁, x₁₄ form a triple that is transformed to the tuple A¹, B¹.

To make the description easily understandable, we assume as an example that the triples of binary data, which are transformed to tuples of ternary data, are each consecutive bits in the sequence x.

In FIG. 6 a the partial circuit F₁ 611 maps the triple x₁, x₂, x₃ of binary values to the tuple of the analog values A¹, B¹. The partial circuit F₂ 612 maps the triple x₄, x₅, x₆ of binary values to the tuple of the analog values A², B², and the partial circuit F_(m) 61 m maps the triple x_(n-2), x_(n-1), x_(n) of binary values to the tuple of the analog values A^(m), B^(m). The function, which is implemented by partial circuit F_(i), is designated with f_(i). In one embodiment all partial circuits F₁, . . . , F_(m) may be identical to partial circuit F 61, as is illustrated in FIG. 6 b, so that there applies F=F₁= . . . =F_(m). Then, the partial circuit implements the function ƒ.

Circuit TrBT 51 is thus implemented in FIG. 6 b as a parallel circuit of m identical partial circuits F 61 with three binary inputs and two analog outputs each.

FIG. 7 a illustrates an embodiment of the circuit TrTB 53 for transforming the values A¹′, B¹′, . . . , A^(m)′, B^(m)′ output by the ternary memory 52 to binary values x′₁, x′₂, . . . , x′_(n). Circuit 53 is composed of m partial circuits R₁ 711, R₂ 712, . . . , R_(m) 71 m for transforming the values A¹′, B¹′ to the values x′₁, x′₂, x′₃, the values A²′, B²′ to the values x′₄, x′₅, x′₆, . . . , the values A^(m)′, B^(m)′ to the values x′_(n-2), x′_(n). The function implemented by the partial circuit R_(i) 71 i is designated with r_(i).

The values A^(i)′, B^(i)′ are analog values which, as explained, are interpreted as ternary values depending on their belonging to the three different intervals W₀, W₁, and W₂. The function implemented by a partial circuit R_(i) is designated with r_(i) for i=1, . . . , m.

In FIG. 7 b, all partial circuits R₁ 711, R₂ 712, . . . R_(m) 71 m of FIG. 7 a were chosen equal to a partial circuit R 71, so that the circuit TrTB 53 is implemented as a parallel circuit of m partial circuits R 71. Each of these partial circuits then implements a function r.

In the following, various embodiments of partial circuits F 61 and R 71 are described.

First of all, the circuit F for implementing the function ƒ is described. The function ƒ is defined by Table 1.

Table 1 illustrates how the tuples A, B of analog values are, in accordance with an embodiment, assigned to the 8 possible triples of binary values 000, 001, . . . , 111 by function ƒ. The corresponding binary variables are designated in Table 1 with x₁, x₂, x₃, so that Table 1 describes the function ƒ for the first three variables. For the respectively following three variables [x₄, x₅, x₆], [x₇, x₈, x_(y)], . . . , the same function ƒ is used. Depending on the belonging of the analog values A, B to one of the intervals W₀, W₁, W₂, they are designated as ternary values A₀, A₁, A₂ or B₀, B₁, B₂, respectively. Function ƒ as determined by Table 1 is implemented by circuits F 61 depicted in FIG. 6 b.

It is generally not necessary that analog values A, B that correspond to the first three binary variables x₁, x₂, x₃ are stored in the first two memory cells of the ternary memory 52. Likewise analog values not necessarily correspond to binary variables x₄, x₅, x₆, that are stored in the following two memory cells, etc. If analog values A, B, which are determined by the values of the binary variables x_(i), x_(j), x_(k), are stored in a pair of memory cells, the binary variables x₁, x₁, x_(k) are called the variables corresponding to the memory cells in which the analog values A, B are stored.

Thus, if, for example, analog values A, B, that are determined by the binary variables x₇, x₁₁, x₂₁, are stored in the second and third memory cells of the ternary memory, the variables x₇, x₁₁, x₂₁ are the binary variables corresponding to the second and third memory cells.

In Table 1, the variables x₁, x₂, x₃ are the binary variables corresponding to the pair of memory cells storing ternary values A, B.

Table 1 describes a first example of a function ƒ that can be implemented by the partial circuit F 61.

TABLE 1 x₁x₂x₃ A B 000 A₀ B₀ 001 A₁ B₂ 010 A₀ B₁ 011 A₀ B₂ 100 A₂ B₁ 101 A₂ B₀ 110 A₂ B₂ 111 A₁ B₀

For instance, the tuple of ternary values A₀, B₀ is assigned by Table 1 or by function ƒ to the triple of binary values 000 (first line of Table 1), and the tuple A₂, B₁ to the triple 100 (5^(th) line of Table 1). The analog values A and B of a tuple of analog values A, B are each stored in a memory cell of the ternary memory 52. The values stored in a memory cell are referred to as the conditions of the memory cell.

Since there exist eight different triples of binary values and nine different tuples of ternary values, one of the tuples of ternary values, according to Table 1 the tuple A₁, B₁, does not occur. This tuple of ternary values is assigned to none of the triples of binary values.

For any of the triples x₁, x₂, x₃ of binary values written into memory Schspei 21, tuple A₁, B₁ is not written into the ternary memory 52. If one writes, for instance, the triple 100 into the memory Schspei 21, the tuple of ternary values A₂, B₁ is written into the corresponding two memory cells of the ternary memory 52.

Due to an error, however, the tuple A₂, B₁ written into the ternary memory 52 may be distorted or falsified to tuple A₁, B₁ when the corresponding memory cells are read, so that on reading from the memory instead of the correct tuple A₂, B₁ the incorrect tuple A₁, B₁ is stored in the corresponding memory cells of the ternary memory 52, and an incorrect value A₁, B₁ and hence also an incorrect value x′₁, x′₂, x′₃ is read.

Although tuple A₁, B₁ is never written into the ternary memory, it is necessary to assign a triple of binary values to this tuple during reading from the memory. In one embodiment, it is of advantage to choose an assignment such that an error correction of the error, which distorted A₂, B₁ to A₁, B₁, can be performed as easily as possible.

Table 2 describes a function r, illustrating how the corresponding triples x₁, x₂, x₃ of binary values may be assigned to tuples A₁, B₁. This function r is implemented by partial circuit R 71 of FIG. 7 b.

TABLE 2 A₀ A₁ A₂ B₀ 000 111 101 B₁ 010 000 100 B₂ 011 001 110

By means of Table 2 one recognizes which triples of binary values are assigned during reading to the tuples of ternary values that are stored in the memory. The triple of binary values corresponding to A_(i), B_(j) is positioned in the field of intersection of the column designated with A_(i) and the row designated with B_(j). Thus, the triple 101 corresponds to the tuple A₂, B₀ and the triple 000 corresponds to the tuple A₁, B₁. In correspondence with Table 2, the triple 000 (left upper field) is assigned to the tuple A₀, B₀, the triple 000 (central field) is assigned to the tuple A₁, B₁, and the triple 001 (central field of the lower row) is assigned to the tuple A₁, B₂. This assignment is in correspondence with Table 1.

If, by Table 1, the tuple of ternary values A₀, B₀ is assigned to the binary triple 000, the triple of binary values 000 is assigned to the tuple of ternary values A₀, B₀ by Table 2. In other words: If the triple of binary values 000 is written into the circuit arrangement Schspei 21, it is stored internally in the ternary memory 52 as A₀, B₀ in two appropriate memory cells and output during reading as a triple of binary values 000. In general, the mapping of triples of binary values to tuples of ternary values as defined by Table 1 is inverted by the mapping of tuples of ternary values to triples of binary values described in Table 2. Moreover, the triple 000 is assigned to the tuple A₁, B₁. For the description of errors in the ternary values or conditions of the memory elements stored in the ternary memory, the term of the contiguous value combination is used. Contiguous value combinations, i.e. tuples of ternary values, are such pairs of value combinations of ternary values that are relatively easy to disturb due to an error into one another.

Two value combinations A_(i), B_(j) and A_(i), B_(k) of ternary values or of conditions of memory cells are called contiguous if k and j differ by 1. Likewise, two value combinations A_(i), B_(j) and A_(i), B_(j) are called contiguous if i and l differ by 1. Thus, the value combinations A₀, B₁ and A₀, B₂ are contiguous, while the value combinations A₀, B₁ and A₁, B₂ are not contiguous.

The assignment in Table 1 is implemented such that there applies:

If the value combination A_(i), B_(j) is assigned to x₁, x₂, x₃ and the value combination A_(l), B_(k) is assigned to x′₁, x′₃, and if A_(i), B_(j) and A_(l), B_(k) are contiguous, then x₁, x₂, x₃ and x′₁, x′₂, x′₃ differ in an odd number of bits. In other words, the value combinations x₁, x₂, x₃ and x′₁, x′₂, x′₃ then differ by 1 or 3 bits.

Thus, triples being adjacent in a row or in a column in Table 2 and corresponding to contiguous value combinations of conditions differ by 1 or 3 bits respectively.

Table 1 describes how the 8 triples of binary values x₁, x₂, x₃ can be mapped to 8 tuples A_(i), A_(j) of ternary values during writing into the memory. No binary values are mapped to the tuple A₁, B₁ during writing. Due to an error in the memory, a tuple of ternary values, for, instance, the tuple A₂, B₁ may be distorted to tuple A₁, B₁, so that tuple A₁, B₁ may occur in the memory although it was not generated intentionally during writing. For reading, the binary value 000 is assigned to the tuple A₁, B₁.

By means of Table 2 one also recognizes that it is not possible to assign to all value combinations of pairs of conditions that are contiguous triples of binary values that differ in one bit only. Thus, the value combination A₁, B₁ has four neighbors, namely the value combinations [A₀, B₁], [A₁, B₀], [A₁, B₂], and [A₂, B₁]. There are, however, only 3 triples, namely [ x ₁, x₂, x₃], [x₁, x ₂, x₃], [x₁, x₂, x ₃] that differ from [x₁, x₂, x₃] in one bit. In Table 2, the pairs of triples of binary values 000 and 111 and 111 and 000 which are assigned to the contiguous value combinations A₀, B₀ and A₀, B₁ or A₀, B₁ and A₁, B₁, respectively, differ by 3 bits each. Such assignment can be used to enable an implementation of an error correction circuit.

Table 3 describes a further embodiment of an assignment of analog values A, B to the possible eight triples 000, 001, . . . , 111 of binary values which variables x₁, x₂, x₃, may take wherein the analog values are again designated as A₀, A₁, A₂ or as B₀, B₁, B₂, respectively, depending on their belonging to one of the intervals W₀, W₁, W₂.

TABLE 3 x₁x₂x₃ A B 000 A₁ B₁ 001 A₂ B₁ 010 A₁ B₀ 011 A₂ B₀ 100 A₀ B₁ 101 A₀ B₂ 110 A₀ B₀ 111 A₁ B₂

By Table 3, tuple A₁, B₁ is, for instance, assigned to triple 000 and tuple A₁, B₂ is assigned to triple 111. According to table 3 tuple A₂, B₂ is assigned to none of the triples, so that this tuple of ternary values can only be stored in the ternary memory 52 if an error has occurred.

Table 4 illustrates an embodiment wherein triples of binary values are assigned to tuples of ternary values.

TABLE 4 A₀ A₁ A₂ B₀ 110 010 011 B₁ 100 000 001 B₂ 101 111 000

If two tuples of ternary values are contiguous, the triples of binary values assigned to them by Table 4 differ in an odd number of bits, wherein at least one pair of triples of contiguous tuples differs in 3 bits. Thus, binary triple 000, which is assigned to ternary tuple A₁, B₁, differs from the binary triple 111, that is assigned to the contiguous tuple A₁, B₂, by three bits.

In the following the advantage that the tuple A₂, B₂ is assigned to none of the triples of binary values is shown.

In one embodiment ternary memory can be a flash memory. If low threshold voltage values (positive to low negative stored charging values on the floating gate) correspond to ternary values A₀ and B₀ stored in the memory cells, medium threshold voltage values (low to medium negative stored charging values on the floating gate) correspond to ternary values A₁ and B₁, and high threshold voltage values (medium to high negative stored charging values on the floating gate) correspond to ternary values A₂ and B₂, a tuple A₂, B₂ can only be stored in the memory cells of the ternary memory 52 if, due to an error, a low or medium threshold voltage value was distorted to a higher threshold voltage value. If the ternary memory is a flash memory, the error may, for instance, also have occurred by incorrect programming.

In the case of analog values that have already been written into the ternary memory and that are, for instance, assumed as threshold voltage values here, the analog value, here the threshold voltage value, will increase rarely only, but will rather be diminished incorrectly due to loss of charge. This is due to the fact that the relatively high incorporated electrical fields occur with the higher charging amounts and hence higher threshold voltage values may result in a loss of negative charge. Thus, a stored tuple A₁, B₂ will only very rarely be distorted incorrectly to the tuple A₂, B₂ since the charge pertaining to A₂ on the floating gate is more negative than that pertaining to A₁. The tuple A₂, B₂ can, however, more easily distort to one of the tuples A₁, B₂ or A₂, B₁ by loss of charge.

Tuple A₂, B₂ is, however, pursuant to the assignment of Table 3, not written into ternary memory 52. So this can only occur in case of a processing error during writing. Accordingly it is of advantage if tuple A₂, B₂ is not assigned to any triple of binary values, as is illustrated in Table 3.

Table 3 reveals that value A₁ is written into a first memory cell of the ternary memory 52 for the allocations 000, 010, and 111. This is exactly the case if the Boolean expression T ₁ = x ₁ x ₂ x ₃ V x ₁ x ₂ x ₃ Vx ₁ x ₂ x ₃ = x ₁ x ₃(x ₂ V x ₂)Vx ₁ x ₂ x ₃ = x ₁ x ₃ Vx ₁ x ₂ x ₃  (4) equals 1.

Correspondingly, Table 3 reveals that A₂ is written into the corresponding memory cell of the ternary memory for the allocations 001 and 011 of x₁, x₂, x₃.

This is the case if the Boolean expression T ₂ = x ₁ x ₂ x ₃ V x ₁ x ₂ x ₃ = x ₁ x ₃  (5) equals 1.

For all other allocations of x₁, x₂, x₃ the corresponding memory cell is allocated with A₀.

Table 3 also reveals that B₁ is written into a corresponding second memory cell of ternary memory 52 for the allocations 000, 001, and 100 of x₁, x₂, x₃.

This is the case if the Boolean expression T ₃ = x ₁ x ₂ x ₃ V x ₁ x ₂ x ₃ Vx ₁ x ₂ x ₃ =x ₂( x ₁ V x ₃)  (6) equals 1.

Correspondingly, Table 3 reveals that B₂ is written into the corresponding memory cell of the ternary memory for the allocations 101 and 111 of x₁, x₂, x₃. This is the case if the Boolean expression T ₄ =x ₁ x ₂ x ₃ Vx ₁ x ₂ x ₃ =x ₁ x ₃  (7) equals 1. For all other allocations of x₁, x₂, x₃ the corresponding memory cell is allocated with B₀.

If the ternary memory 52 is a flash memory, it is well-known that a memory cell in a memory area is only written into after the deletion of the memory area. After deletion, all memory cells of the deleted memory area are set to a value A₀ or B₀, respectively, so that only the values differing from A₀ or from B₀, respectively, have to be written.

FIGS. 8 a, 8 b, 8 c illustrate an implementation of partial circuit F for implementing function F 61 in FIG. 6 b by making use of Tables 3 and 4. The binary inputs are again designated with x₁, x₂, x₃ in FIG. 8 a. The binary inputs x₁, x₂, x₃ are directly mapped to the corresponding analog output values A and B that represent ternary values.

Partial circuit F 61 of FIG. 6 b for implementing the function ƒ is composed of the two partial circuits F¹ 814 and F² 817, as is illustrated in FIG. 8 a. Partial circuit F 61 is illustrated in FIG. 8 a for the first three binary input values x₁, x₂, x₃ and for the first two ternary output values A₁ and B₁ of the circuit TrBT 51 of FIG. 6 b.

First partial circuit F¹ 814 has three binary inputs at which the binary values x₁, x₂, x₃ are available, and one analog input at which an analog value V₁ is constantly available. V₁ is an analog value being in the interval W₁. The partial circuit F¹ 814 has a first analog output at which value A₁=V₁ is output if this output is coupled to the analog input that carries the signal V₁. It comprises a second analog output at which value B₁=V₁ is output if this output is coupled to the analog input carrying analog signal V₁.

For the binary allocations x₁, x₂, x₃ for which T₁= x ₁ x ₃Vx₁x₂x₃=1 is valid, the analog input carrying value V₁ is coupled to the first output carrying the value V₁ then, and for the binary allocations x₁, x₂, x₃ for which T₃= x ₂( x ₁V x ₃)=1 is valid, the analog input carrying value V₁ is coupled to the second output that carries the value V₁ then.

The second partial circuit F² 817 exhibits two binary inputs to which the binary values x₁, x₃ are provided, and one analog input to which an analog value V₂ is constantly provided. V₂ is an analog value in the interval W₂. Partial circuit F² 817 comprises a first analog output at which value A₂=V₂ is output if this output is coupled to the analog input carrying analog signal V₂, and a second analog output at which value B₂=V₂ is output if this output is coupled to the analog input carrying the analog signal V₁.

For binary allocations x₁, x₃ for which T₂= x ₁ x ₃=1 applies, the analog input carrying value V₂ is coupled to the first output carrying value V₂ then, and for the binary assignments x₁, x₃ for which T₄= x ₁x₃=1 applies, the analog input carrying value V₂ is coupled to the second output that carries the value V₂ then.

The first output of the partial circuit F¹ 814 and the first output of the second partial circuit F² 817 are coupled to the first output 815 of circuit F 61 marked with A. This output is, depending on the binary allocation x₁, x₂, x₃ available, coupled to the analog input of the partial circuit F¹ 814 that carries the value 1/E W₁ if T₁=1, or, if T₂=1, to analog input of the partial circuit F² 817 carrying the analog value V₂εW₂, or, if neither T₁=1 nor T₂=1 applies, to none of these analog inputs. For T₁=1 there applies A=A₁, and for T₂=1 there applies A=A₂.

The second output, i.e. B1, of partial circuit F¹ 814 and the second output i.e. B2, of the second partial circuit F² 817 are connected with the second output of the circuit F 61 which is marked with B. This output is, depending on the binary allocation x₁, x₂, x₃ available, coupled to the analog input of the partial circuit F¹ 814 carrying value V₁εW₁ if T₃=1, or if T₄=1, to the analog input of the partial circuit F² carrying the analog value V₂εW₂, or, if neither T₃=1 nor T₄=1 applies, to none of these analog inputs. For T₃=1 there applies B=B₁, and for T₄=1 there applies B=B₂.

Note that in FIG. 6 a, the analog values constantly carrying the values V₁ and V₂ are not illustrated as inputs of the circuit F 61.

FIG. 8 b illustrates an embodiment of an implementation of partial circuit F¹ 814 of FIG. 8 a. Circuit F¹ is constructed of the switches 83, 84, 85, 86, 87, 88, and 810, each comprising one input and two outputs that are referred to as lower output and upper output. These switches are controlled by the binary values x₁, x₂, x₃, x₃, x₃, x₂, x₁. If the binary control value 1, here x₁=1, is input in one of the switches, for instance in switch 83, it couples its input to its upper output. If a binary control value 0 is input, it couples the input to its lower output.

The input of partial circuit F¹ 814 which carries the analog value V₁ is coupled to the input of the switch 83, to the input of the switch 87 and to the input of the switch 810.

The upper output of the switch 83 is coupled to the input of the switch 84. The upper output of the switch 84 is coupled to the input of the switch 85. The lower output of the switch 83 is connected with the input of the switch 86. The lower output of the switch 810 is connected with the lower output of the switch 87 to the line 811, and the line 811 is guided into the input of the switch 88. The lower output of the switch 88 is the second output of the partial circuit F¹ 814 which is marked with B1. The lower output of the switch 86 is connected with the upper output of the switch 85 to a line 812 that forms the first output of the partial circuit F¹ 89 which is marked with A₁.

The connecting lines between the switches are marked in FIG. 8 b with Boolean expressions, so that value V₁ is available on the respective connecting line if the corresponding Boolean expression equals 1. Thus, the connecting line between the switches 83 and 84 is marked with x₁ since the value V₁ is available on this line if x₁=1 applies. The line 811 that implements the connection of the lower outputs of the switches 810 and 87 is marked with x ₁V x ₃ since this expression assumes the value 1 and this line carries the value V₁ if either x₁=0 or x₃=0 is valid. The line coupled to the lower output of the switch 88 is marked with the expression x ₂( x ₁V x ₃). This line carries the value V₁ if T₁= x ₂( x ₁V x ₃).

FIG. 8 c illustrates a possible implementation of partial circuit F² 817 of FIG. 8 a. It comprises switches 81 and 82 with one input and two outputs that are controlled by the binary values x₁ and x₃.

The input of the circuit F² 817 carrying the analog value V₂ is coupled to the input of switch 81. The upper output of the switch 81 is coupled to the input of the switch 82. The lower output of switch 82 forms the first output of circuit F² 817, which is marked with A₂, while the upper output of switch 82 forms the second output that is marked with B₂. The coupling lines between the switches and the outputs are again marked with Boolean expressions. Thus, the connecting line between switches 81 and 82 is marked with x₃ since the value V₂ is available on this line if x₃=1. Correspondingly, the first output line for A₂ is marked with x ₁x₃ since value V₂ is output on this output line if T₂= x ₁x₃=1. The second output line for B₂ is marked with x₁x₃ since the value V₂ is available on this line if T₄=x₁x₃=1.

The pertinent partial circuit R 71 of FIG. 7 b which transforms a tuple of ternary values A′B′ which are read out from ternary memory 52 to a corresponding triple x′₁, x′₂, x′₃ of binary values is illustrated in FIG. 9.

The depicted circuit implements the mapping of tuples of ternary values A′B′ to triples of binary values x′₁x′₂x′₃ as illustrated in Table 5 and which results directly from Table 4.

TABLE 5 A′B′ x₁x₂x₃ A₀B₀ 110 A₀B₁ 100 A₀B₂ 101 A₁B₀ 010 A₁B₁ 000 A₁B₂ 111 A₂B₀ 011 A₂B₁ 001 A₂B₂ 000

Thus, in the first line of Table 5 the triple 110 is assigned to tuple A₀B₀ since the triple 110 is positioned in Table 4 in the left upper field whose column is marked with A₀ and whose row is marked with B₀. In the last row of Table 4, the triple 000 is assigned to the tuple A₂B₂ since the triple 000 is positioned in Table 4 in the right lower field whose column is marked with A₂ and whose row is marked with B₂.

In one embodiment circuit R 71 of FIG. 9 comprises, for instance, a serial connection of digital-to-analog converter DAW 91 with two analog inputs to which analog values A′ and B′ are provided, and m binary outputs at which an m-component binary vector y=y₁, . . . , y_(m) is output, and a downstream combinational circuit Komb 92 with m binary inputs and 3 binary outputs at which the binary values x₁x₂x₃ are output. There applies m≧3.

The digital-to-analog converter DAW may comprise a digital-to-analog converter converting the analog values A′ to two binary values y₁, y₂ and converting signal B′ to two binary signals y₃, y₄, so that in this case m=4. A person skilled in the art will often perform the digital-to-analog conversion by making use of a Gray code, as is proposed already in Steinbuch, K. and Ruprecht, W. Nachrichtentechnik [Communications Engineering], Publishing House Springer, Berlin, Heidelberg, New York, 1967, pp. 339-341. If A₀ and B₀ are each converted to 0, 0; A₁ and B₁ each to 0, 1; and A₂ and B₂ each to 1, 1 then the value table of the combinational circuit Komb 92 of Table 6 results in that in Table 5 A_(i) and B_(j) for j=0, 1, 2 are replaced by the digital tuples y₁, y₂ and y₃, y₄ assigned to them.

TABLE 6 y₁y₂, y₃y₄ x₁x₂x₃ 00, 00 110 00, 01 100 00, 11 101 01, 00 010 01, 01 000 01, 11 111 11, 00 011 11, 01 001 11, 11 000

In Table 6, the output values of the combinatory circuit Komb 92 are defined for 9 input values y₁, y₂, y₃, y₄.

For the remaining 7 values for y₁, y₂, y₃, y₄, which are not listed in Table 6, the output values of the combinatory circuit Komb 92 remain undetermined, and these undetermined or ‘don't-care’ values may be used for circuit optimization.

The binary values y₁, y₂, y₃, y₄ are auxiliary values for reading. They are generated only during reading after the output of analog values A¹′ B′, . . . , A^(m)′B^(m)′ stored in the corresponding memory cells of the ternary memory 52 by means of digitizing by an analog-to-digital converter DAW 91. When writing data into memory Schspei these binary auxiliary values for reading y₁, y₂, y₃, y₄ are not required. Various analog-digital converters may be used to generate m binary auxiliary values for reading y₁, . . . , y_(m).

Another possibility of digital-to-analog conversion of auxiliary values for reading comprises digitizing each of the analog signals A′ and B′ by making use of a 1-of-3 code. If A₀ and B₀ are each converted to 0, 0, 1; A₁ and B₁ each to 0, 1, 0; and A₂ and B₂ each to 0, 0, 1, the value table of the combinational circuit Komb 92 of Table 7 results in that in Table 5 A_(i) and B_(j) for j=0, 1, 2 are replaced by the digital triples y₁, y₂, y₃ and y₄, y₅, y₆ assigned to them. In this case, m=6 is valid. For a particular function ƒ as defined by Table 3 and for a corresponding function r as defined by Table 4, there are different possibilities of option for the auxiliary values for reading y₁, . . . , y_(m) also with different values for m, and that the auxiliary values for reading y₁, . . . , y_(m) are not stored in the ternary memory but have to be generated after reading the ternary values from the ternary memory 52 only.

TABLE 7 y₁y₂y₃, y₄y₅y₆ x₁x₂x₃ 100, 100 110 100, 010 100 100, 001 101 010, 100 010 010, 010 000 010, 001 111 001, 100 011 001, 010 001 001, 001 000

In Table 7, the output values of the combinatory circuit Komb 92 are determined for 9 input values y₁y₂y₃, y₄y₅y₆.

For all 64−7=57 values for y₁y₂y₃, y₄y₅y₆, which are not listed in Table 7, the output values of the combinational circuit Komb 92 remain undetermined. These undetermined or ‘don't-care’ values may be used for circuit optimization.

Since the design of a combinational circuit given as a table of values lies within the knowledge of a skilled artisan. Also the implementation of circuit R 71 as defined by the assignment of a triple x₁, x₂, x₃ of digital values to a tuple A′, B′ of ternary values as in Table 5 lies within the knowledge of the skilled artisan, there is no need to unnecessarily obscure this description with the details of circuit R 71.

FIG. 10 illustrates an embodiment of circuitry for error detection of 1-bit and 2-bit errors. FIG. 10 first of all illustrates the corrector 43 of FIG. 4. Circuit components corresponding to the circuit components in FIG. 4 are designated with the same reference numbers. In addition to corrector 43 described in FIG. 4, a q-bit line 103 carrying the values of the error syndrome s as output by syndrome generator Syndr 45 is coupled to the input of an XOR circuit 101 with q inputs and one output and an OR circuit 102 with likewise q inputs and one output.

XOR circuit 101 outputs parity value P(s) of the components of the syndrome s with P(s)=s ₁ ⊕s ₂ ⊕ . . . ⊕s _(q) OR circuit 102 outputs the OR operation of the components of the syndrome s with OR(s)=s ₁ Vs ₂ V . . . Vs _(q)

Assuming that only correct values of 1-bit errors, 3-bit errors and 2-bit errors are to be distinguished from one another, there applies:

If P(s)=0 and OR(s)=0, then there is no error.

If P(s)=1 and OR(s)=1, then there is a 1-bit error or a 3-bit error.

If P(s)=0 and OR(s)=1, then there is a 2-bit error.

Subsequently the error correction according to the invention is described with an embodiment comprising q=5 check bits c=c₁, . . . , c₅ and k=7 data bits u=u₁, . . . , u₇, so that the code exhibits a length of n=12 bits. The columns of the H-matrix h_(i) with i=1, . . . , 12 all exhibit an odd number of ones. The H-matrix is indicated here in systematic form H=(I ₅ ,P _(5,7)) wherein I₅ is the (5, 5) unit matrix and P_(5,7) a (5, 7) is a parity matrix.

The H-matrix H=h₂, h₁₂) in one embodiment can be

$\begin{matrix} {H = \begin{pmatrix} 1 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 1 \\ 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 0 \\ 0 & 0 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 1 \\ 0 & 0 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 1 \\ 1 & 2 & 3 & 4 & 5 & 6 & 7 & 8 & 9 & 10 & 11 & 12 \end{pmatrix}} & (8) \end{matrix}$

Every column h_(i), i=1, . . . , 12 consists of 5 components, so that the H-matrix consists of 5 rows. Note that for illustration purposes only each column is terminated in the sixth row by an integer number indicating the number of the column.

In the following it is illustrated that there exists a partition of the columns of the H-matrix in w=n/3=12/3=4 sets M₁={h₁, h₂, h₃}, M₂={h₄, h₅, h₆}, M₃={h₇, h₈, h₉}, M₄={h₁₀, h₁₁, h₁₂} with 3 columns each, so that the element-wise XOR sum of the respectively three columns of the H-matrix contained in one of these sets is not a column of the H-matrix. The columns of the H-matrix are arranged such that the first three columns h₁, h₂, h₃ of the H-matrix are elements of the first set M₁, the following three columns h₄, h₅, h₆ are elements of set M₂, the following three columns h₇, h₈, h₉ are elements of set M₃, and the following three columns h₁₀, h₁₁, h₁₂ are elements of set M₄.

In case the columns are initially arranged in some other way, the columns can be rearranged that every three consecutive columns are elements of one of these sets.

Since n=12 is divisible by 3 without remainder, there are w=12/3=4 such sets without any columns remaining during the classification in sets of three elements. If the remainder of the division of n by 3 is 1, there is another set M_(m+1)={h_(n)} comprising one element. Since all columns of the H matrix are different, this additional column H_(n) will not occur again in the H-matrix H. If the remainder of the division of n by 3 is 2, there is another set M_(w+1)={h_(n-1), h_(n)}. The H-matrix H will then have to be chosen such that the element-wise XOR sum h_(n-1)⊕h_(n) does not form a column of the H-matrix.

The element-wise XOR sum of the first three columns k ₁ =h ₁ ⊕h ₂ ⊕h ₃=[1,1,1,0,0]^(T) does not form a column of the H-matrix. Likewise, there applies: The element-wise XOR sum of the following three columns k ₄ =h ₄ ⊕h ₅ ⊕h ₆=[1,1,0,0,1]^(T) does not form a column of the H-matrix. Likewise, there applies: The element-wise XOR sum of the following three columns k ₇ =h ₇ ⊕h ₈ ⊕h ₉=[0,0,1,1,1]^(T) does not form a column of the H-matrix. Likewise, there applies: The element-wise XOR sum of the following three columns k ₁₀ =h ₁₀ ⊕h ₁₁ ⊕h ₁₂=[1,0,0,1,1]^(T) does not form a column of the H-matrix.

For i=1 mod 3 there applies that the XOR sum k_(i)=h_(i)⊕h_(i+1)⊕h_(i+2) does not form a column of the H-matrix.

Such H-matrix may, for instance, be determined as follows:

In a first step the set of all possible columns that are basically suited as columns of the H-matrix are chosen.

These are, for instance, all different columns with m elements or all columns with m elements having an odd number of ones. In the described embodiment with m=5, all 16 columns with an odd number of ones have been chosen as a set of all basically possible columns. If the H-matrix shall be determined in systematic form, the columns with exactly one 1 are chosen as the first 5 columns from the set of all possible columns. These columns no longer form part of this set now. They form the unit matrix I₅ of the H-matrix.

For the first three columns there applies k₁=h₁⊕h₂⊕h₃=[1, 1, 1, 0, 0]^(T) and column k₁ is deleted from the set of possible columns. Since h₄ and h₅ are already determined, from the set of the remaining possible columns, h₆ is now chosen as the 6^(th) column from the set of the remaining possible columns. IN this embodiment this is the column h₆=[1, 1, 0, 1, 0]^(T). For the three columns h₄, h₅, h₆ following the third column there applies k₄=h₄⊕h₅⊕h₆=[1, 1, 0, 0, 1]^(T). Therefore, the column k₄=[1, 1, 0, 0, 1]^(T) is deleted from the set of possible columns of the H-matrix. From the set of the remaining possible columns of the H-matrix, the three columns h₇, h₈ and h₉ are now chosen. There applies k₇=h₇⊕h₈⊕h₉=[0, 0, 1, 1, 1]^(T), and column k₇=[0, 0, 1, 1, 1]^(T) is deleted from the set of possible columns of the H-matrix. From the set of the remaining possible columns of the H-matrix, the three columns h₁₀, h₁₁ and h₁₂ are now chosen. There applies k₁₀=h₁₀⊕h₁₁⊕h₁₂=[1, 0, 0, 1, 1]^(T), and column k₁₀=[1, 0, 0, 1, 1]^(T) is deleted from the set of possible columns of the H-matrix, which is now empty.

If, during the determination of the H-matrix, there results a column k_(j)=h_(j)⊕h_(j+1)⊕h_(j+2) with j=1 modulo 3=1 mod 3, which already exists as a column of the determined columns of the H matrix, one simply has to choose from the set of possible columns of the H-matrix, for instance, instead of the column h_(j+2) another column h′_(j+2) for which this does not apply.

Determining from a set of basically possible columns an H-matrix in which the XOR sums k_(i)=h_(i)⊕h_(i+1)⊕h_(i+2) for i=1 mod 3 do not form columns of the H-matrix lies within the skills of the artisan.

From the H-matrix, the equations for determining the syndrome s=s₁, s₂, s₃, s₄, s₅ result as s ₁ =c ₁ ⊕u ₁ ⊕u ₂ ⊕u ₃ ⊕u ₇ s ₂ =c ₂ ⊕u ₁ ⊕u ₂ ⊕u ₄ ⊕u ₅ ⊕u ₆ s ₃ =c ₃ ⊕u ₂ ⊕u ₃ ⊕u ₄ ⊕u ₅ ⊕u ₇ s ₄ =c ₄ ⊕u ₁ ⊕u ₂ ⊕u ₃ ⊕u ₄ ⊕u ₆ s ₅ =c ₅ ⊕u ₂ ⊕u ₅ ⊕u ₆ ⊕u ₇.

An implementation of these equations as a syndrome generator by making use of XOR gates with 2 inputs and one output is no problem for a skilled artesian and will therefore not be described here in detail.

The function of the decoder is defined by Table 8.

TABLE 8 s₁ s₂ s₃ s₄ s₅ e₁ e₂ e₃ e₄ e₅ e₆ e₇ e₈ e₉ e₁₀ e₁₁ e₁₂ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1

Encoder Cod 41, in FIG. 4, is defined by a generator matrix G of the contemplated code. The determination of a G-matrix in systematic form from an H-matrix in systematic form is known to the person skilled in the art, and is, for instance, described in Lin, S. and Costello, D. “Error Control Coding: Fundamentals and Applications” Prentice Hall, Englewood Cliffs, 1983, pages 54-55.

A generator matrix G in systematic form results directly from the H-matrix H=(I _(q) ,P _(q,k))  (9) of the code in systematic form to G(P _(k,q) ^(T) ,I _(k))  (10) wherein P_(k,q) ^(T) is the transposed (k,q) matrix of the (q,k) matrix P_(q,k) in which the rows of P_(q,k) are the columns of P_(k,q) ^(T).

The G-matrix which in one embodiment can be determined from the H-matrix (8) is

$\begin{matrix} {{G = \begin{pmatrix} 1 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \end{pmatrix}},} & (11) \end{matrix}$ and encoder Cod 11, 41 determines the code words x by x=x ₁ , . . . , x ₁₂ =u·G=(c,u)=(c ₁ , . . . , c ₅ ,u ₁ , . . . , u ₇)

For the check bits c=c₁, c₂, c₃, c₄, c₅ there applies then c ₁ =u ₁ ⊕u ₂ ⊕u ₃ ⊕u ₇ c ₂ =u ₁ ⊕u ₂ ⊕u ₄ ⊕u ₅ ⊕u ₆ c ₃ =u ₂ ⊕u ₃ ⊕u ₄ ⊕u ₅ ⊕u ₇ c ₄ =u ₁ ⊕u ₂ ⊕u ₃ ⊕u ₄ ⊕u ₆ c ₅ =u ₂ ⊕u ₅ ⊕u ₆ ⊕u ₇.

An implementation of an encoder by XOR gates, for instance, with two inputs and one output lies within the knowledge of a person skilled in the art and will therefore not be described in detail here.

The mode of operation of the invention will be described in the following by means of examples. In one embodiment we consider k=7 and n=12. Hence, q=n−k=5. Data bits u=u₁, . . . , u₇=0101111 are, for instance, written into the circuit arrangement according to the invention. The data bits u are available on 7-bit input line 47 in FIG. 4. They are encoded by encoder 41 by applying the G-matrix G of equation (11) to the code word x=u·G=c ₁ ,c ₂ ,c ₃ ,c ₄ ,c ₅ ,u ₁ ,u ₂ ,u ₃ ,u ₄ ,u ₅ ,u ₆ ,u ₇ with u=u₁, u₂, u₃, u₄, u₅, u₆, u₇=0, 1, 0, 1, 1, 1, 1 and c ₁=0⊕1⊕0⊕1=0 c ₂=0⊕1⊕1⊕1⊕1=0 c ₃=1⊕0⊕1⊕1⊕1=0 c ₄=0⊕1⊕0⊕1⊕1=1 c ₅=1⊕1⊕1⊕1=0 so that x=000100101111 and the 12 elements, i.e. the bits of x are output by encoder 41 on the 12-bit line 48. These values are provided to the input of circuit arrangement Schspei 42 and are stored under the address a provided on line 413. The binary values available at the input of the circuit arrangement Schspei are transformed to analog values representing ternary values, stored as conditions in 2·m=8 memory cells of m=4 pairs of memory cells. The stored conditions, i.e. the ternary values, are retransformed to binary values when reading the analog values representing the ternary values.

Storing of data will now be explained in more detail by means of FIG. 5. As described, binary sequence x=000 100 101 111 is provided to the input of circuit arrangement Schspei. In FIG. 5, the input 54 corresponds to this input.

By means of circuit TrBT 51 for transforming a sequence of binary values to a sequence of ternary values, binary sequence x is transformed to sequence A¹B¹, A²B², A³B³, A⁴B⁴ of ternary values. In one embodiment, i.e. as illustrated in FIG. 6 b, circuit TrBT is implemented as a parallel circuit of four equal circuits F 61, wherein circuit F 61 implements function ƒ defined by Table 3. A triple of three, here consecutive, binary values is transformed by the circuit F to a tuple of ternary values that are stored as conditions in a pair of memory cells.

In the contemplated embodiment, and in correspondence with Table 3 the first triple of binary values 000 is transformed to tuple A¹B¹=A₁B₁ of ternary values, the second triple 100 of binary values is transformed to the tuple A²B²=A₀B₁ of ternary values, the third triple of binary values 101 is transformed to the tuple A³B³=A₀B₂ of ternary values, and the fourth triple of binary values 111 to the tuple A⁴B⁴=A₁B₂ of ternary values.

Under address a, the ternary values A₁B₁ are stored in the first pair of memory cells of the ternary memory 52, the ternary values A₀B₁ in the second pair of memory cells of the ternary memory 52, the ternary values A₀B₂ in the third pair of memory cells of the ternary memory 52, and the ternary values A₁B₂ in the fourth pair of memory cells of the ternary memory 52 as conditions.

To begin with, we first consider the case that no error occurs. There applies then P(s)=0 and OR(s)=0.

Then, during reading from ternary memory 52 at address a, the ternary values A₁B₁, A₉B₁, A₀B₂, A₁B₂ are output on the 2·4=8 bit line 58, and they are provided to the input of the circuit TrTB 53.

It is assumed that the circuit TrTB 53, as illustrated in FIG. 7 b, is implemented as a parallel circuit of m=4 partial circuits R 71, each implementing the function r as defined in Table 5. Thus, the partial circuit R, for instance, transforms the tuple of ternary values A₁, B₁ corresponding to the fifth row of Table 5 to the triple 000 of binary values. The binary values 000 100 101 111 are then output via line 56 of FIG. 5 which corresponds to the line 48 in FIG. 4. This sequence of binary values is input via the line 49 of FIG. 4 to syndrome generator Syndr 45 and simultaneously in a first input of XOR circuit 44.

Syndrome generator Syndr 45 outputs the error syndrome s=s₁, s₂, s₃, s₄, s₅ at its q=n−k=12−7=5 bit output, wherein the elements, i.e. the bits, of the error syndrome s are defined as s ₁=0⊕0⊕1⊕0⊕1=0 s ₂=0⊕0⊕1⊕1⊕1⊕1=0 s ₃=0⊕1⊕0⊕1⊕1⊕1=0 s ₄=1⊕0⊕1⊕0⊕1⊕1=0 s ₅=0⊕1⊕1⊕1⊕1=0

Since no error has occurred, the error syndrome equals 0, as expected.

The values of the syndrome, here s=0, 0, 0, 0, 0, are provided to input line 410 of decoder Dec 46. The decoder accordingly outputs, in correspondence with Table 8, the n=12 bit error vector e=0, . . . , 0. The error vector is provided to the second input of the XOR circuit 44 and is connected with x′ to form x^(c)=x′⊕0, . . . , 0=000 100 101 111. The result is output at output line 412.

Now it is described how the circuit arrangement according to the invention behaves in case of an error in ternary memory 52, i.e. the condition of a memory cell is falsified for whatever reason.

We consider the case where a correct condition A₁ is distorted to become condition A₀ in the first memory cell. The tuple A₁B₁, which is stored in the first two memory cells correctly, is contiguous to the tuple of ternary values A₀, B₁. Upon readout, the triple 100 of binary values is, in accordance with Table 4, assigned to this incorrect tuple A₀, A₁, so that the sequence x′=100 100 101 111 is output at output 49 of circuit arrangement Schspei 42. The incorrect sequence x′ differs in one bit from the correct sequence x. This sequence is mapped by the syndrome generator Syndr 45 to the error syndrome 1, 0, 0, 0, 0 that is available the line 410 and hence also at the input of decoder Dec 46. The error syndrome is here equal to the first column of the H-matrix H. For the parity P(s) and for OR(s) there applies now P(s)=1 and OR(s)=1

These values are output on lines 104 and 105 in FIG. 10. Decoder Dec 46 outputs at its output 411 in correspondence with the 2^(nd) line of Table 8 an error vector e=1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 that is connected in the XOR circuit 44 with the sequence x′ to x^(c)=x′⊕e=(1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1)⊕(1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)=(0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1)=x, so the error distorting A₁ to A₀ and resulting in an error in the binary sequence x′ is corrected properly.

In another example, the case is considered that condition B₂ of the 8^(th) memory cell is distorted to B₁. The tuple of ternary values A₁B₁ stored in the 7th and 8th memory cells of ternary memory 52 is contiguous to the corresponding correct tuple A₁B₂. The triple of binary values 000 is assigned according to table 4 to the incorrect tuple A₁, B₁, so this error results in the change of three consecutive bits of the binary sequence x′. For the parity P(s) and for OR(s) there applies now P(s)=1 and OR(s)=1

These values are output via lines 104 and 105 in FIG. 10. An error distorting a tuple of ternary values to a tuple of contiguous ternary values is detected from the fact that P(s)=1 and =OR(s)=1.

At output 49 of circuit arrangement 42, the bit sequence x′=000100101000 is now output, from which the error syndrome s=s₁, s₂, s₃, s₄, s₅=1, 00, 1, 1 is derived which equals the XOR sum of the last three columns of the H-matrix H. This error syndrome does not form a column of the H-matrix H.

By means of decoder 46, the error vector e=0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 is, in accordance with the last line of Table 8, assigned to this syndrome, said error vector being XORed in the XOR circuit element-wise with x′=0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0 to x^(c)=x′⊕e=x, so this error is detected and corrected properly.

An error, that distorts two tuples of ternary values to two respectively contiguous tuples of ternary values results in P(s)=0 and OR(s)=1, which are output on lines 104 and 105 in FIG. 10.

Now, there will be explained for one embodiment how the pertinent tuple of ternary values can be determined directly from a triple of binary values.

A triple 111 of binary values is directly mapped to the tuple of ternary values A₁B₂ in correspondence with the last line of Table 3. The triple of binary values is described by variables x₁, x₂, x₃, irrespective of the fact for which pair of memory cells the tuple of ternary values is determined.

We first consider circuit of FIG. 8 b, which implements the circuit F¹ 814 of FIG. 8 a. Although in the instant case it is a matter of the 7^(th) and 8^(th) memory cells, the corresponding binary variables are, as mentioned, designated with x₁, x₂, x₃, so that x₁=1, x₂=1, and x₃=1 applies. Switches 83, 84, and 85 each connect their input with their upper output, so that the input carrying the analog value V₁ is directly connected with the output 812 and A₁=Since V₁ belongs to the interval W₁, A₁εW₁ correctly applies. The switches 86, 87, 88, and 810 also connect their input with their upper output, so that no further connection of the input carrying the value V₁ exists with an output.

Now, the circuit of FIG. 8 c which implements the circuit F² of FIG. 8 a will be considered. Since x₁=x₃=1, the switches 81 and 82 each connect their input with their upper output, so that B₂=V₂ and B₂εW₂ applies, since V₂εW₂. As illustrated in FIG. 8 a, the output of circuit F¹, which is marked with A₁, and the output of circuit F², which is marked with A₂, are coupled to line 815 carrying value A=A₁εW₁, since this output is only coupled to the input of circuit F¹ carrying the analog signal V₁. The output of circuit F¹, which is marked with B₁, and the output of circuit F², which is marked with B₂, are coupled to line 816 carrying value B=B₂εW₂, since this output for x₁=x₃=1 is only coupled to the input of circuit F² which carries the analog signal V₂. 

The invention claimed is:
 1. A memory device for storing a block of binary data u of length k, k being an integer, k>2, comprising: an encoder configured to receive the binary data, and configured to encode the block of binary data u of length k into encoded binary data x of length n, n≧k, wherein the encoder uses an error correcting code C with a code distance d≧3; and a storage component coupled to the encoder, and configured to receive the encoded binary data x and output binary output data x′ of length n, wherein the storage component is configured to transform binary data x into ternary data, store the ternary data as ternary states in ternary memory cells of a ternary memory, and transform the ternary data into binary data x′ when the ternary data is retrieved from the ternary memory; and a corrector coupled to the storage component, the corrector configured to receive binary data x′ from the storage component, and correct errors in the received binary data x′ caused by errors in the states of the ternary memory cells of the ternary memory.
 2. The memory device of claim 1, wherein the error correcting code C is a linear block code with an (k−n) generator matrix G and a (q,n) parity check matrix H with q=n−k.
 3. The memory device of claim 2, wherein the corrector comprises a syndrome generator, a decoder, and a combiner circuit, wherein the syndrome generator is configured to generate an error syndrome s=s₁, . . . , s_(q) of length q with q=n−k based on the received binary data x=x₁′, . . . , x_(n)′ wherein s ^(T) =H·(x ₁ ′, . . . , x _(n)′)^(T) and wherein s^(T) is a column vector of length q of the elements s₁, . . . , s_(q) and (x₁′, . . . , x_(n)′)^(T) is the column vector of length n of the elements wherein H=(h₁, h₂, . . . , h_(n)) is the parity check matrix of code C with the column vectors h₁, . . . , h_(n), wherein the column vectors are pairwise different where the columns h₁, h₂, . . . , h_(n) of the H-matrix H consist of n/3 groups of three columns {h_(i1),h_(i2),h_(i3)}, . . . , {h_(i[n-2]),h_(i[n-1]),h_(in)} if n is divisible by 3 without remainder, and wherein the columns h₁, h₂, . . . , h_(n) of the H-matrix H consist of (n−2)/3 groups of three columns each {h_(i1),h_(i2),h_(i3)}, . . . , {h_(i[n-4]),h_(i[n-3]),h_(i[n-2])} and a group of two columns {h_(i[n-1]),h_(in)} if n−2 is divisible by 3 without remainder, and wherein the columns h₁,h₂, . . . , h_(n) of the H-matrix H consist of (n−1)/3 groups of three columns each {h_(i1),h_(i2),h_(i3)}, . . . , {h_(i[n-3]),h_(i[n-2]),h_(i[n-1])} and a group of a single element {h_(in)} if (n−1) is divisible by 3 without remainder, such that the component-wise XOR sum of all columns of each group of columns of the parity check matrix H do not form a column of the parity check matrix H if the corresponding group contains at least two columns.
 4. The memory device of claim 3, wherein binary data bits corresponding to the columns of a group of columns of the H-matrix, for which the componentwise XOR-sum of that columns does not form a column of the H-matrix, are stored as ternary values in a pair of memory cells of the memory device.
 5. The memory device of claim 1, wherein information is stored in a ternary memory cell as a continuous physical value or state Z of that memory cell which, in dependence on the membership of the state Z of that memory cell to one of non-overlapping intervals W₀, W₁, W₂ of the continuous physical values, represents a ternary value Z₀, Z₁ or Z₂ with Z₀<Z₁<Z₂, where Z₂ is maximal and where Z₀ is minimal.
 6. The memory device of claim 5, wherein Z represents a threshold voltage of a nonvolatile memory cell.
 7. The memory device of claim 1, wherein in the storage component a pair of ternary memory cells is provided for storing one triple of binary data.
 8. The memory device of claim 7, wherein the storage component comprises circuitry configured to transform a triple of binary data into a tuple of ternary data, wherein the circuitry exhibits at least three binary inputs and two ternary outputs, and wherein the circuitry for a triple of binary data x₁,x₂,x₃ outputs a tuple ternary values Z¹,Z², and for another, different triple of binary data x₁′,x₂′,x₃′ the circuitry outputs another, different pair of ternary values Z^(1′),Z^(2′), wherein Z¹, Z² and Z¹, Z² belong to different pairs of ternary values W_(i),W_(j) and W_(k),W_(l), with (W_(i),W_(j))≠(W_(k),W_(l)), and wherein if the pairs of ternary values are neighbouring, then x₁,x₂,x₃ and x₁′,x₂′,x₃′ differ by one or by three bits, whereby the pairs Z¹,Z² and Z^(1′),Z^(2′) are neighboring if a first of their components belongs to the same interval and the second component belong to two contiguous intervals W_(K) and W_(L) of physical values where K and L differ by
 1. 9. The memory device of claim 8, wherein the circuitry for transforming a triple of binary data to a tuple of ternary data is configured to transform none of the triples 000, 001, 010, 011, 100, 101, 110, 111 of binary values into a tuple of ternary data Z_(i), Z_(i), wherein Z_(i) corresponds to a minimal physical value stored in a ternary memory cell.
 10. The memory device of claim 8, wherein the circuitry for transforming a triple of binary data to a tuple of ternary data is configured to transform none of the triples 000, 001, 010, 011, 100, 101, 110, 111 of binary values into a tuple of ternary data Z_(i), Z_(i), wherein Z_(i) corresponds to a maximal physical value stored in a ternary memory cell.
 11. The memory device of claim 10, wherein the columns of the parity check matrix H=(h₁, . . . , h_(n)) are ordered such that h₁, . . . , h_(n)=h_(i1), . . . , h_(in).
 12. The memory device of claim 11, wherein the columns h₁, . . . , h_(n) of the parity check matrix H comprises an odd number of ones.
 13. The memory device of claim 12, wherein the device outputs an error signal indicating a 2-bit error if the syndrome s does not equal 0 and if the number of ones of components of the syndrome is even and indicating a 1-bit error or a 3-bit error if the number of ones of the components of the syndrome is odd.
 14. A memory device for storing binary data, comprising: an encoder configured to receive a block of binary data u of length k, k>2, and encode the received binary data using a linear error correcting code thus producing a block of encoded binary data x of length n, n>k; a storage component, coupled to the encoder and comprising binary-to-ternary transformer circuitry configured to transform triples of encoded binary data x into tuples of ternary signals, and further comprising ternary memory configured to store the ternary signals, and comprising ternary-to-binary transformer circuitry configured to transform tuples of ternary signals into triples of binary signals x′, and wherein the storage component is configured to output binary signals x′; and corrector circuitry coupled to the output of the storage component, and configured to determine an error vector e based on the output binary signals x′ of the storage component; and a circuit coupled to the output of the storage component and to the output of the corrector circuitry, and configured to combine the binary signals x′ and error vector e to produce a corrected output of the memory device.
 15. The memory device of claim 14, wherein the corrector circuitry comprises: a syndrome generator configured to generate an error syndrome s of length q=n−k based on a parity check matrix and the output of the storage means x′; and a decoder circuit configured to generate the error vector e of length n based on the error syndrome s.
 16. The memory device of claim 15, wherein the circuit coupled to the output of the storage component and the output of the corrector circuitry is configured to XOR-combine the error vector e with the binary signals x′ to correct the data as output by the storage component.
 17. The memory device of claim 16, wherein in the storage component two ternary memory cells are provided for storing triples of binary data and where the storage component comprises circuitry configured to transform a tuple of ternary data into a triple of binary data, the circuitry exhibiting two ternary inputs and three binary outputs, wherein the circuitry for a tuple of ternary data Z¹, Z² outputs a triple of binary data x₁,x₂,x₃, and if for another, different tuple Z^(1′), Z^(2′) of ternary data the circuitry outputs a triple x₁′,x₂′,x₃′, of binary data, wherein Z¹, Z² and Z¹′, Z²′ belong to different pairs of intervals W_(i),W_(j) and W_(k),W_(l) with (W_(i),W_(j))≠(W_(k),W_(l)) and wherein the pairs of ternary states are neighboring, then x₁,x₂,x₃ and x₁′,x₂′,x₃′ differ by one or three bits, whereby the pairs Z¹, Z² and Z¹′, Z²′ are neighboring if a first component of the first pair and a first component of the second pair belong to the same interval and the second component of the first pair and the second component of the second pair belong to different intervals W_(K) and W_(L) where K and L differ by one.
 18. The memory device of claim 17, wherein the decoder is configured to generate an error or correction vector e=e₁, . . . , e_(n) with binary components e₁, . . . , e_(n) and with e_(i)=1 and e_(j)=0 for j≠t, if the error syndrome s is s=h_(i), where h_(i) is the t-th column of the parity check matrix H of the code C and, if n is divisible by 3 without remainder and if iε{1, 4, . . . , n−2} and if the error syndrome s is s=h_(i)⊕h_(i+1)⊕h_(i+2) . . . , where h_(i), h_(i+1) and h_(i+2) are the i-th, the (i+1)-th and the (i+2)-th columns of the parity check matrix H of the code C, then the components e_(i), e_(i+1), e_(i+2) of the error vector e are equal to one and all the other components of the error vector e are equal to zero; if the remainder of the division of n by 3 is equal to 2 and if iε{1, 4, . . . , n−4} and if the error syndrome s is s=h_(i)⊕h_(i+1)⊕h_(i+2) then the components e_(i), e_(i+1), e_(i+2) of the error vector e are equal to one and all the other components of the error vector e are equal to zero; if the remainder of the division of n by 3 is equal to 2 and if the error syndrome s is s=h_(n-1)⊕h_(n), then the components e_(n-1) and e_(n) of the error vector e are equal to one and all the other components of the error vector e are equal to zero; if the remainder of the division of n by 3 is equal to 1 and if iε{1, 4, . . . , n−3} and if the error syndrome s is s=h_(i)⊕h_(i+1)⊕h_(i+2) then the components e_(i), e_(i+1), e_(i+2) of the error vector e are equal to one and all the other components of the error vector e are equal to zero; and if the remainder of the division of n by 3 is equal to 1 and if the error syndrome s is s=h_(n), then the component e_(n) of the error vector e is equal to 1 and all the other components of the error vector are equal to zero, wherein the components e₁, . . . , e_(n) of the error vector are component-wise XORed with the corresponding components x₁′, . . . , x_(n)′ of the binary data x′=x₁′, . . . , x_(n)′.
 19. A method for storing a block of binary data u of length k, k being integer, k>2, comprising: receiving the binary data in an encoder, and encoding the block u into e encoded binary data x of length n, n≧k, using an error correcting code C with a code distance code d≧3; and storing the encoded binary data x in a storage component coupled to the encoder, wherein the storing comprises transforming binary data x into ternary data and storing the ternary data as ternary states in ternary memory cells, and reading the ternary data from the ternary memory cells, and transforming the ternary data into binary data x′; and correcting errors in the binary data x′ caused by errors in the states of the ternary memory cells.
 20. The method of claim 19, wherein the error correcting code C is a linear block code with an (k−n) generator matrix G and a (q,n) parity check matrix H with q=n−k.
 21. The method of claim 19, wherein information is stored in a memory cell as a continuous physical value or state Z of that memory cell which, in dependence on the membership of the state Z of that memory cell to one of non-overlapping intervals W₀, W₁, W₂ of the continuous physical values, represents a ternary value Z₀, Z₁ or Z₂ with Z₀<Z₁<Z₂, where Z₂ is maximal and where Z₀ is minimal. 